1. Technical Field
The present invention relates to a method for manufacturing a semiconductor package.
2. Description of the Related Art
Recently, the electronic industry has developed slim, thin and light products having multi-function and high performance at low costs. One of the technologies accomplishing such trends is a packaging technology. With the development in the electronic industry, the usage of a package of electronic equipment mounted with a semiconductor chip has been abruptly increased and research into a package technology related thereto has been actively conducted.
At this time, most of the semiconductor packages have been accomplished such that one package is made by connecting a semiconductor chip to a printed circuit board by a wire bonding. This board is called a board on chip (BOC). In such a BOC structure, the semiconductor package may be designed only with a printed circuit board that includes only a single metal layer, and as a result, is in a superior position in terms of price competitiveness of a semiconductor package.
FIGS. 1 to 6 are cross-sectional views showing a method for manufacturing a semiconductor package according to the prior art in a process sequence.
As shown in FIG. 1, a copper clad laminate configured of an insulating layer 1 and a copper layer 2 is provided and a through hole 3 is machined on the copper clad laminate for interlayer conduction. The through hole is generally formed using CNC drilling or laser drilling.
Thereafter, as shown in FIG. 2, a chemical copper plating process and an electrical copper plating process are performed, thereby forming a copper plating layer 4 over the copper clad laminate.
Then, as shown in FIG. 3, the inside of the through hole 3 is filled with a plugging ink 5 and a plating is performed on the panel, thereby forming a plating layer 6 that is to be thick.
Then, as shown in FIG. 4, the plating layer 6 is selectively etched, thereby forming a circuit pattern 7.
Then, as shown in FIG. 5, a solder resist 8 is applied to both surfaces of the copper clad laminate formed with the circuit pattern 7 and an opening part is formed so that a portion of the circuit pattern 7 is opened.
Then, as shown in FIG. 6, after a slot 9 into which a wire 30 is to be inserted is machined, a solder ball 10 is formed on a pad part of the circuit pattern 7 and a semiconductor chip 20 is mounted on the substrate using the wire 30, thereby implementing a semiconductor package 50.
In order to implement the semiconductor package according to the prior art, the through hole should be formed on the copper clad laminate for interlayer conduction and the electrical/chemical copper plating processes should also be performed, which causes increase in manufacturing costs.
In addition, when a semiconductor chip is connected to a printed circuit board using a wire to implement a high-volume/high-density semiconductor package, there is a limit in receiving density of semiconductor chips and an increase in the manufacturing costs of a printed circuit board due to a demand for a BOC of two-layer or more.